Notes on Using Interrupts on Mid-Range PIC Processors
One of the major advantages of the mid-range PIC family as compared to the
earlier 16C5x family is the availability of interrupts. However, due to
the minimalist nature of the PIC there are a few gotchas as compared to other
The following notes were written as advice to someone who was having trouble
using interrupts from Timer 0 (also known as RTCC) on a PIC16C71, but would
generally apply to any of the interrupt sources.
- Make sure you turn on the GIE bit and the T0IE bit in the INTCON register
when your code is prepared to deal with interrupts.
- Clear the T0IF bit before turning on the enable bits (as in hint 1), or
you may get an immediate unexpected interrupt because the timer may have
already overflowed previously.
- Make sure your interrupt handler saves and restores W and STATUS properly.
It is tricky to restore without changing STATUS; the SWAPF instruction
must be used. The 16C7x data sheet has suggested code in section 14.6.
Also, you may need to save other registers such as FSR or PCLATH if your
interrupt handler changes them.
Note that on some of the larger PICs (but not the 16C71), the RAM portion
of the register file is not duplicated between the two register banks.
This requires particular care when saving the W register in the interrupt
handler, as the same address must be reserved for this purpose in both
banks, and it will not be possible to determine in advance which of the
two locations will actually be used on any given interrupt. Since the
interrupt return code restores the STATUS register before restoring the W
register, it will not matter which bank was used.
See the data sheet for details.
- If your mainline code ever changes the active register bank (such as to
access TRIS registers, etc.) while interrupts are enabled, the interrupt
handler must set the bank select bit as appropriate for the registers that
it will access. Since the register bank select bit is part of the STATUS
register, it will be restored if you restore STATUS as in hint 3 above.
- The interrupt handler must clear the T0IF bit in the INTCON register
before it returns in order to clear the interrupt condition. Otherwise
the interrupt handler will get called continuously.
- The interrupt handler must use the RETFIE instruction to return, or the
GIE bit will stay clear and you won't get any more interrupts after the
- If your code ever needs to turn off the GIE bit (global interrupt enable),
make sure you read Microchip application note 576. There can be a problem
if an interrupt happens during the execution of the instruction that turns
It is generally easier to turn off only the specific interrupt
enable bit(s) that you care about, such at T0IE.
error in Microchip Application Note 556
which claims that an interrupt during an instruction that changes the PCL
can return to the wrong instruction. Microchip has finally confirmed that
the application note is wrong.
If you're using the ByteCraft C compiler, you might want to look at this
email from Kenneth Furge, in which he provides
a wrapper for interrupt handlers.
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Last updated December 16, 1996
Copyright 1995, 1996 Eric Smith