IBM 5100 Portable Computer

Introduced in 1975, the 5100 was IBM's first production personal computer (six years before the PC!). The 5100 has an integral CRT display, keyboard, and tape drive. It was available with APL, BASIC, or both, and with 16, 32, 48, or 64 Kbytes of RAM.

Memory capacity Programming Language
16 Kbytes A1 B1 C1
32 Kbytes A2 B2 C2
48 Kbytes A3 B3 C3
64 Kbytes A4 B4 C4

Available options:


The 5100 has an internal CRT (five inch diagonal) which displays 16 lines of 64 characters. Because the characters are so small, IBM provided a three-position switch to allow the user to select the display of all 64 characters of each line, or only the left or right 32 characters (interspersed with spaces).

Normally the display is generated from the buffer in main memory at addresses 0x0200..0x05ff. There is a front-panel switch which makes the unit display the first 512 bytes of main memory (addresses 0x0000..0x01ff) in hexadecimal for diagnostic purposes, mainly to observe the processor registers.

Mass storage:

Mass storage was provided by a quarter-inch cartridge tape drive using DC300 cartridges to store 204 Kbytes. Tapes were written in 512-byte records. There are several file types including BASIC programs, APL workspaces, and data.

System Software:

On a 5100 with both languages, the user's choice of language is selected by a toggle switch on the front panel!

Instead of being written in the native microcode instruction set of the processor, the 5100's language interpreters are written for more sophisticated "virtual machines", and the microcode emulates those machines. This was done in order to economize on the amount of ROS needed to implement the language interpreters, and perhaps to speed the product development. The APL microcode emulates a subset of the System/360 instruction set, while the BASIC microcode emulates the System/3.2

The APL interpreter was derived from APLSV.

Hardware Technology:


Most of the logic circuitry in the 5100 is built using a TTL-compatible 134-gate bipolar gate array technology called "Dutchess". Each chip has 60 three input NAND gates, 40 four-input NAND gates, and 34 two-input NOR off-chip drivers. The gate propogation delay times are about 10 ns. The chips are packaged in square metal cans.


The 5100 uses a board-level microprocessor1 called "PALM" (for "Put All Logic in Microcode"), generally referred to as the "controller" in IBM documentation. The board contains thirteen of the square metal-can packages, along with three conventional DIP-packaged parts and one round metal can part.

PALM uses 16-bit vertical microinstructions. The average microinstruction execution time is 1.75 µs.

Microinstructions can directly reference sixteen 16-bit general-purpose registers. Register zero is the microinstruction pointer, also known as the program counter. There are four banks of registers, one bank per interrupt level, for very fast interrupt context switching. The four banks of registers are also addressable as the first 128 bytes of RAM. (The first 128 bytes of the actual RAM cards is not available.)

There are three interrupts, so there are four processor levels, 0-3, with level 0 executing when no interrupt is pending. Since each level has its own program counter, there is no concept of an interrupt vector. The processor will remain at a given level as long as the hardware interrupt request for that level is active (and no higher-level request is active). Interrupt handlers are thus normally written as loops.

The ALU is eight bits wide. Despite the fact that the registers are 16 bits wide, PALM provides few 16-bit arithmetic or logical operations. However, some 8-bit operations may cause a carry or borrow from the high byte of a register.

The procesor has a 16-bit address bus. The memory is byte-addressable, for a maximum directly-addressable capacity of 64 Kbytes. Each byte of memory has a parity bit, so the memory data busses are 18 bits.

Branches can be effected any instruction which writes or alters register zero. One particularly interesting trick allows the creation of a single-instruction infinite loop by clearing register zero. In this case, register zero serves both as the program counter, and as the instruction word pointed to by the program counter. An all zeros word decodes as an instruction to subtract two from register zero. After the instruction is fetched, the PC is incremented by two, then the instruction subtracts two from it again, leaving it at zero. This single-instruction loop technique was used when code running at level zero (non-interrupt) needed to wait for an interrupt to be serviced. The interrupt handler would then write a new value to location zero, which is NOT the interrupt handler's PC, since the handler is running at a non-zero level. Once the hardware interrupt is cleared, level zero gets control again starting from the new PC value.

Read Only Storage (ROS)

There are three kinds of ROS (more commonly known as ROM or Read Only Memory) in the 5100.

The "control ROS" is part of the PALM processor and is used to decode the microinstructions. It is organized as 256 words of 32 bits.

The "executable ROS" is directly addressable by the processor, and contains the microinstructions that are directly executed. There is 16K*18 of microcode for the diagnostic and bringup routines, I/O supervisor and control routines, and the virtual machine interpreter for BASIC. Another 16K*18 of microcode provides the virtual machine interpreter for APL.

The "nonexecutable ROS" is accessed as an I/O device by the processor, and contains the code interpreted by the virtual machines, namely the APL and BASIC language interpreters. The nonexecutable ROS uses n-channel MOSFET chips storing 48 Kbits each, with an access time of approximately 2 µs.

The nonexecutable ROS is divided into three regions:

Read/Write Storage

The RAM memory consists of one to four pairs of boards of 8 Kbytes each, using NMOS RAM chips and separate bipolar drivers and sense amplifiers. The Roberson articles claim that the memory is implemented using 1 Kbit MOSFET RAM chips, but it appears that they actually use 2 Kbit chips. Each board has nine RAM modules each of which apparently contains four chips. This memory has an access time of approximately 300 ns, and a cycle time of approximately 450 ns.

Del Cecchi wrote:

The memory technology almost certainly was "Reisling" which used 2k chips packaged 4 to a 1/2 inch stacked module with external sense amp bit driver modules. A typical riesling card as used in system/34 and system/32 had 8k Bytes on a "2 wide 3 high" card, although there was a later card that was 16KB.
He also wrote that the 8K card was code-named "Snoopy", and the 16K card "Barton". The 5110 uses the 16K cards, which frees up some backplane slots for other purposes.

Display Controller

The display controller is the only 5100 device to use Direct Memory Access (DMA), which IBM refers to as "cycle-stealing". The display is memory mapped. Microcode can disable the display during calculations in order to make more memory bandwidth available to the processor.

Related Systems:


The 5100 was based on the design of an earlier proof-of-concept system called SCAMP, for "Special Computer, APL Machine Portable". SCAMP was also based on the PALM processor, but used a Norelco (Philips) compact cassette drive instead of the 3M cartridge. SCAMP emulated an IBM 1130 minicomputer in order to run APL\1130. SCAMP is in the Smithsonian Institution.


The 5100 product line was later expanded to include the 5110, which supported external 8-inch floppy disk drives, and the 5120 with built-in floppy drives. The 5120 also seems to be known as a 5110 Model 3.

In 1980 IBM introduced the System/23 DataMaster, based on the Intel 8085 processor.

In 1981 IBM introduced the IBM PC, Type 5150, based on the Intel 8088 microporcessor. Although there had been many personal computers before, the introduction of the IBM PC finally was seen in the corporate world as validating the concept. To this day, over 90% of desktop computers are still largely compatible with the original IBM PC.


1 The term microprocessor was used to mean a processor that executes microcode in order to interpret a higher-level instruction set, rather than the now common usage to refer to a processor implemented on a single monolithic integrated circuit.

2 Emulation of System/3 for BASIC confirmed by Joey Tuttle in his talk at Vintage Computer Festival 6.0, Mountain View, California, 13-Oct-2003.


Related Web Sites:

Thanks to Del Cecchi, Russell P. Holsclaw, Greg Pfister, and Joey Tuttle for providing technical information.

Time Travellers Need IBM 5100 Computers!

From 2000-2001, John Titor claimed to be a time traveller sent form 2036 to 1975 to fetch an IBM 5100 in order to solve problems with legacy software in 2036 (before Unix systems fail in 2038). He stopped in 2000 to warn us of a civil war that would start in the US in 2005 and culminate in World War III in 2015. He claimed that there was some special hidden feature in the 5100:
In 2036, it was discovered (or at least known after testing) that the 5100 computer was capable of reading and changing all of the legacy code written by IBM before the release of that system and still be able to create new code in APL and basic.

On the John Titor web site, select "5100 Computer" in the "Posts by Topic" pulldown menu.

If you have 5100 computers that you'd like to contribute to his cause, I don't know how you can get them to him. On the other hand, I'm still trying to find a working A or C model 5100 (with APL), or any 5100 model (working or not) for spare parts. My 5100 model C1 has a bad APL ROS module.

Last updated July 27, 2004

Copyright 1999, 2000, 2002, 2003, 2004 Eric Smith

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