In 1981, Intel announced a revolutionary new microprocessor family called the iAPX-432 MicroMainframe. The iAPX-432 had a very advanced capability-based architecture, with hardware and microcode support for multitasking, multiprocessing, and fault tolerance.
Initially the family consisted of a two-chip General Data Processor, and a single-chip Interface Processor. Later Intel added a Bus Interface Unit and a Memory Control Unit.
A brief introduction to the iAPX-432 may be found in the CS 460 Final Project report by David King, Liang Zhou, Jon Bryson, and David Dickson. More detail is available in Chapter 9 of Capabiliy-Based Computer Systems by Henry M. Levy.
In the early days of Usenet, the newsgroup "net.micro.432" was devoted to discussion of the iAPX-432. Never a high-volume newsgroup, it was probably lost in the Great Renaming of 1985.
Unfortunately the raw computing performance of the iAPX-432 proved to be below that of competing microprocessors, and Intel discontinued the iAPX-432 product line in 1986.
Nowdays it's very difficult to find detailed technical information on the iAPX-432. Intel received about fifteen US patents relating to the iAPX-432, but much of the technical details such as the object data structures and instruction set changed between the time of the patent application and customer shipment. So while they're not as accurate as the official architecture manuals, they are at least generally similar to the release 1 architecture, and provide some details that were never available elsewhere, such as the internal microarchitecture of the GDP and IP.
Although many companies evaluated the iAPX-432, as far as I know the only commercial product offering based on the iAPX-432 from any company other than Intel was a board set for Multibus systems from the English company High Integrity Systems. HIS also contracted with Intel to continue the development and maintenance of the Ada compiler.
WANTED! -- Components -- Packaging -- Releases -- Documentation -- Hardware -- Software -- Books -- Papers -- Theses -- Web Pages -- Humor
Any iAPX-432 chips, boards, systems, software, manuals, schematics, documentation, archives of the net.micro.432 newsgroup, or anything else 432 related.
Even if I already have a particular piece of documentation or software, I'd like to get other versions of it, as different software versions and documentation editions supported different releases of the components.
Software development on the 432 also required the following items, which I'm also looking for:
At a minimum, I'm willing to pay postage and/or copying costs. If you can lend me materials to copy, I'll pay postage both ways. I'm willing to purchase hardware or trade for it.
Eventually I hope to secure permission from Intel to scan the documentation and redistribute docs and software on the web to any interested parties.
Note: in the lists and tables below, that I do not actually have any of the items unless specifically noted.
Initially Intel introduced three iAPX 432 components, the 43201 and 43202 which together formed a General Data Processor (GDP), and the single-chip 43203 Interface Processor (IP).
Much of the press surrounding the introduction of the iAPX 432 made it sound like it was a three-chip processor, and quoted a combined transistor count for the three chips. However, this doesn't really make sense since there was no particular relationship between the number of GDPs and the number of IPs in a system.
In 1983 Intel introduced the 43203 Bus Interface Unit (BIU) which acts as a crossbar switch, and the 43204 Memory Control Unit (MCU). These components made it much easier to build large fault-tolerant systems with multiple memory busses.
One of Intel's published papers on the iAPX 432 suggests that the initial objective for the clock rate was 10 MHz (for the IP at least). However, the earliest components actually were shipped with a 4 MHz speed grade. The official speed grades were eventually 5, 7, and 8 MHz.
|part number||description||price, quantity 1K, early 1984|
|5 MHz||7 MHz||8 MHz|
|43201/43202||General Data Processor||$169||$295||$521|
|43204||Bus Interface Unit||$49||$86||$122|
|43205||Memory Control Unit||$108||$190||$271|
The 432 components were among the first to be fabricated using Intel's "HMOS" high-density NMOS process. The 432 used several innovative design concepts:
|part number||die size (mils)||device placements||actual devices|
|43201||318 x 323||110K||60K|
|43202||366 x 313||49K||37K|
|43203||358 x 326||60K||49K|
|43204||285 x ?||65K|
|43205||340 x ?||84K|
The iAPX 432 components were initially offered in a ceramic leadless QUIP package, but later Intel switched to a JEDEC-standard 68-contact leadless chip carrier.
The 432 architecture went through three major releases. The processor components were reissued for each architectural release, and for "dot" releases to correct bugs.
Release 1 of the components was somewhat buggy. Some features were completely unusable (e.g., process time-slicing, the "insert ordinal" instruction). This release was used on the iSBC 432/100 evaluation boards to run Object Programming Language (OPL) and Object Builder.
Release 2 made various minor architectural changes needed to support fault recovery, and fixed most of the bugs of Release 1.
Release 3 was a major architectural change intended to improve performance. The biggest change is that every memory segment could have both a data and an access part, so there is no longer a distinction as to the "base type" of a segment (data or access). Many objects that formerly needed two memory segments (one access and one data) now only need one.
|1.0||1981||Original release, with significant bugs. Only supported by Object Programming Language and Object Builder, but not by Ada compiler or iMAX operating system|
|2.0||Bug fixes, and new larger Fault Data Area supporting better fault handling|
|3.0||Major revision to architecture; memory segments allowed to comprise a data part and an access part, rather than requiring two separate segments. Processes use chains of preallocated context objects.|
|3.2||August 1983||stable architecture: GDP Architecture Reference Manual 171860-004 states that Intel expects any further releases of the components beyond release 3.2 to be limited to correcting errors, improving implementation, or making upward-compatible extensions to the architecture.|
|3.3||Believed to be the final internal release. AFAIK, it was not shipped to customers, but was used in-house at Intel and Siemens for software development for the P7/Gemini/BiiN operating system (code-named Osiris).|
|have copy||order number||date||title||notes|
|121565||Mainframe Link for Distributed Development User's Guide|
|171773||iSBC 432/100 Processor Board Schematic Diagram|
|171819-001||Getting Started on the Intellec 432/100|
|*||171819-003, Rev. C||Getting Started on the Intellec 432/100|
|*||171820-001||iSBC 432/100 Processor Board Hardware Reference Manual|
|*||171821-001||Introduction to the iAPX 432 Architecture|
|171823-001||Object Programming Language User's Manual|
|*||171823-002, Rev. B||Object Programming Language User's Manual|
|171826||iSBC 432/100 Processor Board Assembly Drawing|
|*||171858-001 Rev. B||The iAPX 432 Object Primer|
|171859-001||Object Builder User's Guide|
|*||171859-003 Rev. C||Object Builder User's Guide|
|*||171860-001||January 1981||iAPX 432 General Data Processor Architecture Reference Manual||Preliminary, Release 1.0 GDP components, phone-book edition|
|171860-002||October 1981||iAPX 432 General Data Processor Architecture Reference Manual||Advance partial issue, revised for Release 2.0 GDP components|
|171860-002||February 16, 1982||iAPX 432 General Data Processor Architecture Reference Manual|
|171860-003||October 1982||iAPX 432 General Data Processor Architecture Reference Manual||Advance partial issue, revised for Release 3.0 GDP components|
|photocopy||171860-004||January 1984||iAPX 432 General Data Processor Architecture Reference Manual||Completed manual for Release 3.2 GDP Components|
|*||171861-001||System 432/600 32-Bit Extensible Computer System data sheet|
|*||171863-001||April 1981||iAPX 432 Interface Processor Architecture Reference Manual||Partial Issue|
|*||171863-001||July 1981||iAPX 432 Interface Processor Architecture Reference Manual||Release 1.1 Components|
|171863-002||December 1981||iAPX 432 Interface Processor Architecture Reference Manual||Update of terminology; correction of errata|
|171863-003||December 1981||iAPX 432 Interface Processor Architecture Reference Manual||Update for release 2.0 and 2.1 components|
|171863-003||August 1982||iAPX 432 Interface Processor Architecture Reference Manual||Integration of Change Sets 1 and 2 into manual|
|photocopy||171863-004||January 1984||iAPX 432 Interface Processor Architecture Reference Manual||Update for release 3.0 Components|
|171866-001||iMAX 432 Advance Information Sheet|
|171867-001||Intel 432 System Summary, Manager's Perspective|
|171868-001||Intellec Series III/432 Development System Data Sheet|
|171869-001||Reference Manual for the Ada Programming Language|
|*||171869-002||Reference Manual for the Ada Programming Language||includes Intel's Appendix F|
|171870-001||Intel 432 Cross Development System VAX Host User's Guide|
|*||171871-001||Engineering Specifications for the iAPX 432 Extensions to Ada||obsoleted by "Reference Manual for the iAPX 432 Extensions to Ada"|
|*||171873-001 Rev. A||iAPX 43201 iAPX 43202 VLSI General Data Processor data sheet||preliminary|
|171873-002||iAPX 43201 iAPX 43202 VLSI General Data Processor data sheet||obsoleted by order number 590125?|
|*||171874-001 Rev. A||iAPX 43203 VLSI Interface Processor data sheet||preliminary|
|171874-002||iAPX 43203 VLSI Interface Processor data sheet||preliminary||obsoleted by order number 590130?|
|171954-001||Introduction to the Intel 432 Cross Development System|
|*||171963-001||INTELLEC 432/100 Evaluation and Education System data sheet|
|172040||iAPX 43201/43202 Component Errata Sheet|
|172043||Problem Report Form|
|172097||Intel 432 Cross Development System Workstation Reference Manual|
|*||172098-001||System 432/600 System Reference Manual|
|172099-001||System 432/600 Diagnostic Software User's Guide|
|172100||System 432/600 Hardware Reference Manual Volume 1|
|172101||System 432/600 Installation and Maintenance Manual|
|172103||iMAX 432 Reference Manual|
|172172||System 432/600 Hardware Reference Manual Volume 2|
|172174||Asynchronous Communication Link User's Guide|
|*||172283-001||Reference Manual for the iAPX 432 Extensions to Ada|
|draft||172283-002||Reference Manual for the iAPX 432 Extensions to Ada|
|172299-001||iAPX 432 Interface Processor Architecture Reference Manual change package 1|
|172300-001||iAPX 432 Interface Processor Architecture Reference Manual change package 2|
|photocopy||172487-001||December 1982||iAPX 432 Interconnect Architecture Reference Manual|
|172866||iAPX 43204/43205 Data Sheet||obsoleted by order number 210963?|
|*||172867-001||Electrical Specifications for iAPX 43204 BIU and iAPX 43205 MCU (preliminary)|
|210963-001 Rev. A||iAPX 43204 iAPX 43205 Fault Tolerant Bus Interface and Memory Control Units data sheet||preliminary|
|590125||iAPX 43201/43202 General Data Processor Data Sheet|
|590130||iAPX 43203 Interface Processor Data Sheet|
|photocopy of draft||iAPX 432 Components User's Guide|
|photocopy||September 1981||432 Architecture Workshop||Version 2.5|
Precise document names unknown:
|have copy||order number||title||author||publication||date|
|*||AR-166||Understand the Newest Processor to Avoid Future Shock||Jack Hemenway and Robert Grappel||EDN||April 29, 1981|
|AR-167||A methodology for VLSI chip design||J.A. Bayliss, D.L. Budde, W.W. Lattin, J.R. Rattner, W.S. Richardson||Lambda||second quarter 1981|
|photocopy||AR-282, 230711-001||Two chips endow 32-bit processor with fault-tolerant architecture||C. B. Peterson et al.||Electronics||April 7, 1983|
|photocopy||AR-283, 230721-001||Intel iAPX 432 -- VLSI building blocks for a fault-tolerant computer||Dave Johnson, Dave Budde, Dave Carson, and Craig Peterson||AFIPS 1983 National Computer Conference Proceedings||July 1983|
System 432/600 Building Blocks
|Category||part number||description||quantity included in System 432/670|
|Data Processor Modules||SBC 432/601||General Data Processor board||2|
|I/O Modules||SBC 432/602||Interface Processor board||1|
|SBC 432/603||Interface Processor Link board||1|
|Memory Modules||SBC 432/604||Memory Controller board||1|
|SBC 432/606||128 Kbyte dynamic RAM storage board with ECC||0|
|SBC 432/607||256 Kbyte dynamic RAM storage board with ECC||2|
|Backplanes||SBC 432/610||6 slot system bus backplane (3 processor, 1 memory controller, 2 memory)||0|
|SBC 432/611||12 slot system bus backplane (5 processor, 1 memory controller, 6 memory)||1|
|SBC 432/612||18 slot system bus backplane (6 processor, 1 memory controller, 10 memory, 1 test/monitor)||0|
|SBC 432/615||6 slot MULTIBUS backplane||1|
|SBC 432/616||12 slot MULTIBUS backplane||0|
|Cardcages||SBC 432/620||6 slot cardcage||0|
|SBC 432/621||12 slot cardcage||0|
|SBC 432/622||18 slot cardcage||0|
|Chassis||SBC 432/630||Enclosed, powered, and cooled chassis with 18 slot cardcage||1|
|Accessories||SBC 432/635||System bus extender card||0|
|SBC 432/636||Interfae processor link cable kit (external, shielded)|
|SBC 432/637||Interfae processor link cable kit (internal, ribbon)|
|SBC 432/638||Interfae processor link cable kit (external, 6 ft. shielded)|
The System 432/670 includes 432/600-series products as listed above, and also an iSBC 86/12A card to serve as an Attached Processor, an iSBC 340 EPROM daughterboard (16 Kbyte), and an iSBC 300 DRAM daughterboard (32 Kbyte).
I have two iSBC-432/100 evaluation boards, but they are missing all of the socketed chips, including the 43201 and 43202 GDP chips. They're also missing the retaining clips for the QUIP packages. And I don't have any of the software for the 432/100.
I have a single iSBC-432/602 IP board with a release 2.1 IP chip (43203), but it is tagged "temperature sensitive".
And I have a large wire-wrapped board which is alleged to be the wire-wrapped breadboard prototype implementation of the 432 GDP (from before the two-chip implementation as the 43201 and 43202). I don't have any authoritative confirmation (other than the seller's word) that this is what the board really is, but it contains a lot of 82S100 FPLAs, so it seems plausible. The board is still in Oregon, but I'll try to get a photo of it the next time I'm there.
Note that building breadboard prototypes of microprocessors went out of style in the early eighties, because the chips were getting so complex that it would take longer to debug the prototype. Instead, the industry has increasingly relied on simulation. The 432 developers used separate architectural, microcode, logic, and circuit-level simulation tools developed in-house on a DECsystem-10.
|have copy||order number||title|
|172000-xxx||OPL-432 system files, single density|
|172002-xxx||OPL-432 workspace files, single density|
|172001-xxx||OPL-432 system files, double density|
|172003-xxx||OPL-432 workspace files, double density|
Cross Development System - written in Pascal for DEC VAX host running either VMS or BSD Unix:
Series III Development System - written in PL/M-86:
Native - written in Ada:
Currently I have images of the following official release tapes:
and these unofficial tapes:
Wanted: any 432 software of any kind or version, but expecially:
It is lucky for all of us that Intel's 432 processor project never made it back in the early eighties. Otherwise a really horrible Intel architecture might have taken over the world. Whew!
-- Steve Friedl
From: email@example.com (,,,) Subject: Roswell's impact on Computer Science (Was: Bell Labs) Date: 11 Dec 1997 00:00:00 GMT Message-ID: <firstname.lastname@example.org> References: <email@example.com> Organization: The University of Iowa Newsgroups: alt.folklore.computers > > >but the > >military was actually able to boot some of the surviving alien computers. > >Since Bell Labs had extensive capabilities in computer analysis, the alien > >computers were sent there. > > What processor did the alien computers use? What kind of storage did they > have? I spent some time at Bell Labs (Department 1227 (old numbersing system), Murray Hill), and I still have occasional contacts in that world. My understanding is that the computers from the Roswell New Mexico crash are very similar to the Pentium, and that the OS they run is very close to being a version of Windows. As I understand the Roswell story, nobody could even begin the reverse engineering efforts until we had scanning electron microscope technology, and then, the chips were totally incomprehensible until the early 1970's. Fortunately, this was shortly after the UNIX design was set in stone, and it took years to reverse engineer enough of the chip architecture to begin work on disassembling the OS code. Some of the alumni of this project joined Intel shortly after the IAPX 432 hit the streets, and their arrival with what management interpreted as an advanced design was what drove Intel to abandon research on modern capability-based computer architectures and concentrate instead on the bizarrely irrational x86 family of architectures. The fabrication technology reverse engineered from the Roswell chips was indeed advanced, but the architectural fallout is another matter! By the mid 1980's, the funding for continuing the reconstruction of the Roswell OS dried up, and the programmers from that project had to look elsewhere for work. Some of these programmers were snapped up by Microsoft for work on the system that eventually was named Windows 95. Overall, I'd estimate that the fallout of the reverse engineering efforts on the Roswell microprocessors have set computer science in the united states back a good 20 years. Too many good people have spent too many years of their lives attempting to deal with these truly screwy machines. No wonder the starships they ran crashed at Roswell! The technology of these machines may have been advanced, but the alien designers of these machines were not good engineers and had a very bad notion of top-level design! Doug Jones firstname.lastname@example.org
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Last updated May 12, 2015
Copyright 1999, 2000, 2001, 2005, 2014, 2015 Eric Smith