Last updated January 27, 2010
Copyright 2002, 2004, 2010 Eric Smith
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| opcode | mnemonic | operation | notes | ||
|---|---|---|---|---|---|
| binary | hex | internal | external | ||
| 0000 | 0 | NOP0 | - | pulse FLG0 | |
| 0001 | 1 | LD | RR := (DATA and IEN) | - | |
| 0010 | 2 | LDC | RR := not (DATA and IEN) | - | |
| 0011 | 3 | AND | RR := RR and (DATA and IEN) | - | |
| 0100 | 4 | ANDC | RR := RR and not (DATA and IEN) | - | |
| 0101 | 5 | OR | RR := RR or (DATA and IEN) | - | |
| 0110 | 6 | ORC | RR := RR or not (DATA and IEN) | - | |
| 0111 | 7 | XNOR | RR := RR xnor (DATA and IEN) | - | |
| 1000 | 8 | STO | DATA := RR | if OEN pulse WRITE | |
| 1001 | 9 | STOC | DATA := not RR | if OEN pulse WRITE | |
| 1010 | A | IEN | IEN := DATA | - | |
| 1011 | B | OEN | OEN := DATA | - | |
| 1100 | C | JMP | - | pulse JMP | |
| 1101 | D | RTN | skip next instruction | pulse RTN | skip necessary because in a typical hardware implementation, a subroutine call will push the current address rather than an incremented address |
| 1110 | E | SKZ | if RR = 0, skip next instruction | - | |
| 1111 | F | NOPF | - | pulse FLGF | |
Most MC14500B systems will route the RR output to one of the selectable inputs. This provides an easy way to complement RR, and to load 1 into IEN or OEN. Alternatively, the a contant 1 may be provided as one of the selectable inputs.
Simple MC14500B systems do not need to support branching. OEN can be used as a means of implementing conditional expressions.
If the program is smaller than the memory size, the remainder of memory can be filled with NOP instructions. Or FLG0, FLGF, or JMP can be wired to reset the program counter.
I've written a VHDL description of the MC14500B. However, it has not been tested. There is no warranty. Note that the code is NOT in the public domain.
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Last updated January 27, 2010 Copyright 2002, 2004, 2010 Eric Smith |
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