PDP-10 Model Information

In 1991 Joe Smith posted to alt.folklore.computers an old file of information on the different PDP-10 models. I have taken the liberty of reformatting parts of it to HTML for convenient browsing, and appending some comments below.

Joe's web site now has a more up-to-date table.
-- Eric Smith (no relation)

From: jms@tardis.Tymnet.COM (Joe Smith)
Newsgroups: alt.folklore.computers
Subject: PDP-10: how many different models?
Message-ID: <1828@tardis.Tymnet.COM>
Date: 12 May 91 08:35:52 GMT
Reply-To: jms@tardis.Tymnet.COM (Joe Smith)
Organization: BT Tymnet, San Jose, CA
Summary: a bunch

I ran across an old file of mine that listed the various modles of PDP-10 that DEC sold. It's incomplete, as it was written 8 years ago, before the 1095 and 2065 became reality. And it does not include 3rd-party compatibles, such as the Systems Concepts SC30M, SC40M, and Foonly F3 and F4. It's missing the non-DEC pagers as well.

I'd like to collect the missing data, then try to reformat this file so that it fits in 80 columns again (it is 132 cols wide now).

This is a list of the PDP-10 processors as I understand them. Much of the information has yet to be verified.
Joe Smith, 21-Oct-83
PDP-10 Features 1050 1070 1080 1090PA 1090PV 1091 2020 2040PA 2040PV 2050PA 2050PV 2060 "C" "R"
Model-B backplane ucode -- -- No No Yes Yes -- No Yes No Yes Yes Better Yes
Clock speed nanoseconds async async 40 40 33 33 50 40 33 40 33 33 33 33
Extended Sections No page None None None 32 32 1 None 32 None 32 32 32 32
G-floating No DF No No No Yes Yes ? No Yes No Yes Yes Yes Yes
RH20 internal channels No No No Yes Yes Yes No Yes Yes Yes Yes Yes Yes CI
Size of Cache -- -- 2048 2048 2048 2048 512 0 0 2048 2048 2048 4096 2048
I/O bus or Unibus I/O I/O I/O I/O I/O I/O Uni No IOB No IOB No IOB No IOB Option Option NI
Internal memory No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes
Size of cabinets Tall Tall Tall Tall Tall Tall Short Short Short Short Short Short Short Jupiter
Console Front-End None None 11/40 11/40 11/40 11/40 8080 11/40 11/40 11/40 11/40 11/40 11/40 11/40
Bootstrap Device -- -- DECtape DECtape DECtape DECtape Magtape Floppy Floppy Floppy Floppy Floppy Floppy Floppy
Runs TOPS-10 7.01 No Yes Yes Yes Yes Yes Yes No No No No Maybe Maybe No
Runs TOPS-10 7.02 No No No No Yes Yes Yes No No No No Maybe Maybe No
Runs TOPS-10 7.03 No No No No Yes Yes Yes No No No No Maybe Yes Yes
Runs TOPS-20 rel 4 No No No No No Maybe Yes Yes Yes Yes Yes Yes Yes No
Runs TOPS-20 rel 5 No No No No No Maybe No Yes Yes Yes Yes Yes Yes No
Runs TOPS-20 rel 6 No No No No No Maybe No No No No No Yes Yes Yes

The "Model-A backplane" has 1280 words of 96 bit microcode. "Model-B backplane" is 2048 words of microcode. The "Model-C" machine will be a KL10-E with only 2048 words of microcode, but will have 4096 words cache and double pager buffer (1024 instead of 512). The "Model-R" machine is the "FCC-KL", a KL10-E in "Jupiter" cabinets with space enough for CI (HSC/RA81) and NI (Ethernet).

A 2040 is a 2050 without cache, a 2060 is a 2050-PV with MOS memory. A 2060 with an I/O bus is identical to a 1091 painted orange. A 1090 is a 1080 with internal channels. 1090, 2040, and 2050 come with either Model-A or Model-B backplanes. Extended addressing and G-floating both require a Model-B backplane for the microcode (the 2020 uses extended addressing but is limited to a single section). The 1090T was created for ARPANET, it is a blue PDP-20 (floppies instead of DECtapes). 7.02 and Rel 6 require extended addressing. The KA has no paging hardware, therefore it cannot run 7-series monitors or TOPS-20.

1080 KL10-A(PA) running TOPS-10
1088 Dual processor (1080) system
1090 KL10-B(PA) or KL10-D(PV) running TOPS-10
1090T KL10-BC(PA) running TOPS-20 (ARPANET systems only, 1090 with floppies)
1091 KL10-E(PV) with cache and DIB20 I/O bus adapter running TOPS-10
1092 KL10-E(PV) with cache and MOS memory running TOPS-10 (there is no longer any distinction between 1091 and 1092)
1099 Dual processor (1090) system
2040 KL10-C(PA) or KL10-E(PV) without cache running TOPS-20
2050 KL10-C(PA) or KL10-E(PV) with cache running TOPS-20
2060 KL10-E(PV) with MOS memory and cache running TOPS-20

Designation PV Boot Cache DTEs RH20s IO bus Used in
KL10-A No DECtape Yes 1 0 Yes 1080 (no internal channels, uses RH10)
KL10-B No DECtape Yes 4 8 Yes 1090 Model-A
KL10-BC No Floppy Yes 4 8 Yes 1090T (ARPANET)
KL10-C No Floppy Option 4 8 No 2040 Model-A, 2050 Model-A
KL10-D Yes DECtape Yes 4 8 Yes 1090 Model-B
KL10-E Yes Floppy Option 4 8 Option 1091, 2050 Model-B, 2060 Model-B
KL10-fast Yes Floppy Bigger 4 8 Option "Model-C"
KL10-FCC Yes Floppy Yes 4 ? CI/NI "Model-R"

Joe Smith (408)922-6220 | SMTP: jms@tardis.tymnet.com or jms@gemini.tymnet.com
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I think the 1091 column in Joe's first table may have a few incorrect entries. I've been told that a 1091 han a KL10-E CPU in a short cabinet, and uses a floppy as a boot device rather than DECtape. This would be consistent with the claim that a 1091 is a 2060 with an I/O bus and painted blue.

The 1095 and 2065 are apparently the 1091 and 2060 with the cache (and paging?) upgraded to an MCA25.

The KL10 main CPU logic with the old (MCA20) cache is called a KL10-PV. With the MCA25 it is a KL10-PW.

The KL10-PV prints list the following variants:
Variant Cache Internal Channels
KL10-AA, -AB yes no
KL10-BA, -BB, -BC, -BD yes yes
KL10-CA, -CB no yes
-- Eric Smith

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Last updated September 23, 1998

Copyright 1996, 1998 Eric Smith


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