The Western Digital Pascal Microengine, which uses microcode to interpret UCSD Pascal p-code, was announced in late 1978. 1
The Pascal Microengine chipset is designated WD9000, and is a specific mask-programmed version of the MCP1600 chipset. The MCP1600 was originally developed for the DEC LSI-11 (announced in 1975). The WD9000 uses different microcode and different translation PLAs than the LSI-11. The WD9000 chipset consists of five chips:
The MICROMs are part number CP2171-xnn, with x being A for ceramic packaging or B for plastic packaging, and nn being a mask pattern number. The MICROMs can be dumped electrically, and I've done so, using the breadboard apparatus seen here, along with a logic analyzer.
The Pascal Microengine microcode went through multiple revisions over its product life, with known MICROM sets including -10/12/13, -14/15/16, -14/15/17, and -14/15/18. I have dumped all of the known Pascal Microengine MICROMs other than -16, which I don't have. The raw dumps are here:
I've written a microcode disassembler in Python, available on github:
A partially annotated disassembly of the -14/15/18 MICROM set is also on github:
A description of most of the microarchitecture and details of the microinstruction set are available in the DEC LSI-11 Writable Control Store (WCS) user's guide, available online courtesy of Bitsavers:
The microcode is difficult to interpret without having the contents of the "translation arrays", two PLAs embedded in the control sequencer chip (CP2161-x02). The LSI-11 WCS manual makes mention of the translation arrays, but doesn't give a very detailed description of them.
The function of the PLAs is to detect certain microinstruction addresses, and based on those, the contents of an interrupt register, and a translation register, cause jumps or subroutine returns that are not represented in the microcode ROMs, in order to decode and dispatch macroinstructions and interrupts. The PLAs are described in section 4.3.3 of the Alpha Micro AM-100 Technical Manual, available online courtesy of Mike Noel's Virtual Alpha Micro project and Alpha Mico:
There is no known way to dump the translation arrays electrically. Joe Britt and Al Kossow had a photomicrograph of a CP2161 made, which was useful to identify the general layout of the die, but was not of high enough resolution to dump the PLA contents. A partial floorplan of the CP2161 can be seen in this image:
The first PLA consists of Array 1 (AND plane) and Array 2 (OR plane), and the second PLA consists of Array 3 and Array 4. These collectively take up more than 25% of the die area, and are the large fairly regular arrays mostly to the left of the vertical centerline, in order from Array 1 near the center to Array 4 near the left edge. The CP2161 has a smaller PLA in the lower right corner, which it is not necessary to dump in order to interpret the microcode.
The AND plane of PLA 2 is divided into two sections, of which one section accepts the translation register as input, and the other section accepts the interrupt register. I refer to these as Array 3A and Array 3B, respectively.
I sent a CP2161-B02 to John McMaster to decap and photomicrograph, and he has made available the resulting images.
A small portion of the PLA 1 AND plane can be seen here. I was somewhat surprised to find that WD chose to use diffusion mask programming rather than the more typical metalization mask.
I manually transcribed the contents of the four arrays:
I wrote two Python programs to process the PLA transcriptions:
The Python programs output the PLA contents in one of two forms, selectable by command-line option: human-readable (somewhat) and simulator input:
I've written an MCP1600 simulator, not yet published, and using the CP2171-14/15/18 MICROM dumps and the CP2161-B02 PLA dumps, it has successfully executed the first 30 macroinstructions (UCSD p-code instructions) of the PDQ-3 boot ROM. (The PDQ-3 uses the WD9000 chipset.) It's not yet generally useful, but the source code is available on github:
I've also been working on a UCSD release III.0 p-code disassembler, and that is also available on github:
1. At the time of announcement, the design was apparently not finalized, as the announcement states that there are four chips including two microcode ROMs, while as shipped, it has five chips including three microcode ROMS. Mention is also made of the microcode including "micro-diagnostics", which are not present in the shipped products. ↩
Last updated February 6, 2016
Copyright 2016 Eric Smith