The Parallax Propeller Microcontroller


The Parallax Propeller is a powerful and flexible micro controller available in DIP, QFP, and QFN packages.

The "native" languages of the Propeller are SPIN and PASM. The Propeller JVM is implememnted using both languages. Spin like Java is a byte-code interpreted language. The Propeller ASM language is used to interpret Spin and Javelin Java byte-codes.

Spin is an object.method language which does not offer inheritance, shared object references, or polymorphism. Despite these minor shortcomings, Spin is a capable and flexible language that fits the Propeller nicely.

The Propeller can be programmed in Spin/PASM, Basic, C ANSI-C89, Javelin Java and other languages. An emulated GNU tools effort is underway.

Propeller P8x32a Features/Collateral:

  • 8 independent CPU cores (COGS)
  • 2K each per core exclusive RAM
  • 2 counter/timers per CPU core
  • Per CPU core video serializer
  • 32KB shared RAM or "HUB"
  • 32KB shared boot/table ROM
  • CPU core semaphore spin-locks
  • CPU core round robin HUB access
  • Internal/External clock modes
  • Flexible Brown-out modes
  • Flexible reset modes
  • Large Open Source Software collection
  • Friendly and helpful User Forum
  • Propeller Downloadable Material
  • Books available at Amazon and Parallax
  • Educational Material
  • Easy Educational Partnerships



    • The Parallax Propeller is a unique micro controller. It is unique because it is so different from other micro controllers. While some of the differences are seen as weak points with respect to adoption by many who come to expect certain things from micro controllers, the differences are strengths to those of us who enjoy or don't mind learning new things.

    Mythical Propeller Weaknesses:

  • No interrupts.
  • High event activation time.
  • Small CPU Core memory.
  • Too slow.
  • Too small.
  • No dedicated hardware peripherals.

    • Propeller Realities:

  • Multiple CPU cores make interrupts obsolete.
  • Multiple CPU timer/counters can notice events in less than 200ns.
  • Cores can be used for language interpreters.
  • Combined parallel performance is up to 160 MIPS (20 MIPS per core).
  • There is always an application too big for any micro-controller.
  • Software based peripherals are far more flexible.